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MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC S3067 OVERVIEW
The S3067 transceiver implements SONET/SDH and WDM serialization/deserialization, and transmission functions. The block diagram in Figure 4 shows the basic operation of the chip. This chip can be used to implement the front end of WDM equipment, which consists primarily of the serial transmit interface and the serial receive interface. The chip handles all the functions of these two elements, including parallel-to-serial and serial-to-parallel conversion, clock generation, and system timing. The system timing circuitry consists of management of the data stream and clock distribution throughout the front end. S3067 has the ability to bypass the internal VCO with an external source and also with the receive clock. The device generates 14/15, 15/14, 16/17 and 17/16 clocks based upon the received clock and an external clock to incorporate the FEC capability. The dividers support the first two rates shown in Table 4. The S3067 is divided into a transmitter section and a receiver section. The sequence of operations is as follows:
S3067
Transmitter Operations: 1. 16-bit parallel input 2. Parallel-to-serial conversion 3. Serial output Receiver Operations: 1. Serial input 2. Serial-to-parallel conversion 3. 16-bit parallel output Internal clocking and control functions are transparent to the user. S3067 Supports six different code rates, besides the normal rate, for each of the four operating modes.
Suggested Interface Devices
AMCC AMCC S3076 S3062 OC-48 Clock Recovery Device OC-48 Performance Monitor
Table 3. FEC Select
FEC 0 0 1 1 0 0 1 1 0 0 1 1 2 1 1 1 1 0 0 0 0 VCO Divider 17 16 15 14 17 16 15 14 RSCLK Divider 16 17 14 15 X X X X
Table 2. Data Rate Select
RATESEL 0 0 0 1 1 RATESEL 1 0 1 0 1 Operating Mode OC-3 OC-12 OC-24/GBE/FC OC-48
0 1 0 1 0 1
Table 4. FEC Modes
Error Correcting Capability 8 bytes per 255-byte block 7 bytes per 255-byte block 6 bytes per 255-byte block 5 bytes per 255-byte block 4 bytes per 255-byte block 3 bytes per 255-byte block Code Rate showing Bandwidth Expansion due to code words & FSB 255/238 = 7.14% increase 255/240 = 6.25% increase 255/242 = 5.37% increase 255/244 = 4.51% increase 255/246 = 3.66% increase 255/248 = 2.82% increase Example of increased input clock frequency for STS-48/STM-16 (MHz) 155.52*255/238 = 155.52 * 15/14 = 166.63 155.52*255/240 = 155.52 * 17/16 = 165.24 155.52*255/242 = 163.87 155.52*255/244 = 162.53 155.52*255/246 = 155.52 * 85/82 = 161.21 155.52*255/248 = 159.91
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S3067
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Figure 4. S3067 Transceiver Functional Block Diagram
PHINIT VCO CLOCK
TX
LOCKDET 155MCKP/N 19MCK
FECSEL[2:0] RATESEL[0:1] REFCLKP/N POCLK (Internal) RLPTIME FECSEL2 CAP1 CAP2 TESTEN SLPTIME BYPASS PIN[15:0] PICLKP/N 16
3 2 CLOCK SYNTHESIZER CLOCKS
TIMGEN
PCLKP/N PHERR
16:1 PARALLEL TO SERIAL
TXDP/N D TSDP/N
BYPASSCLKP/N
TXCLKP/N TSCLKP/N N
LLEB
KILLRXCLK
RX
D TIMGEN POCLKP/N
RSDP/N
TXDP/N (Internal)
D
D R
1:16 SERIAL TO PARALLEL
16 POUT[15:0]
RSCLKP/N TXCLKP/N (Internal) DLEB SQUELCH
SDTTL SDLVPECL
RSTB IVREF
OVREF
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September 17, 2002/ Revision A
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Figure 5. Clock Synthesizer
VCO PD LPF VCOCLK
S3067
REFCLK
RSCLK
N
RSCLK Divider
FECSEL 2 FECSEL (0-1) Where N = 14/15/16/17 M = 14/15/16/17 RSCLK VCOCLK = N M
M
VCO Divider
A high on FECSEL2 selects RSCLK divided by N. A low on FECSEL2 selects the REFCLK. The REFCLK or RSCLK divided by N is divided by 1/M (multiplied by M) in the loop. The value of M and N can be selected by FECSEL0 and FECSEL1. When FECSEL2 = 0, VCOCLK = REFCLK * M. The user must select the proper value of REFCLK and M to get the desired VCOCLK frequency. When FECSEL2 = 1, VCOCLK = (RSCLK * M) / N. The user must select the proper M/N ratio (with FECSEL0 and FECSEL1) to get the desired VCOCLK value. (See Tables 3 and 4.)
Example: OC-48 FEC capability of 8 bytes per 255-byte block. Required VCOCLK = 2.6656 GHz. Method 1: Required VCOCLK = 2.6656 GHz FECSEL2 = 0, selects REFCLK FECSEL0 = 1 and FECSEL1 = 0, selects VCO divider(M) = 16 REFCLK = 2.6656 GHz / 16 = 166.60 MHz VCOCLK = REFCLK / (1/M) = 166.60 * 16 = 2.6656 GHz Method 2: Required VCOCLK = 2.6656 GHz FECSEL2 = 1, selects RSCLK FECSEL0 = 0 and FECSEL1 = 0, selects VCO divider(M) = 17 and RSCLK divider(N) = 16 RSCLK = (2.6656 * 16) / 17 = 2.5088 GHz VCOCLK = RSCLK / N / (1/M) = 2.5088 GHz / 16 * 17 = 2.6656 GHz.
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S3067
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
The divide by `N' and divide by `M' provide the counters required to support error correcting capability. The values of `N' and `M' can be selected by FECSEL lines. The loop filter generates a VCO control voltage based on the average DC level of the phase discriminator output pulses. A single external clean-up capacitor is utilized as part of the loop filter. The loop filter's corner frequency is optimized to minimize output phase jitter.
S3067 TRANSCEIVER FUNCTIONAL DESCRIPTION
Transmitter Operation
The S3067 transceiver chip performs the serialization stage in the processing of a transmit SONET STS-48/ STS-24/STS-12/STS-3/GBE/FC data stream depending on the data rate selected. It converts 16-bit parallel data to bit serial format. A high-frequency bit clock can be generated from a 131.25 MHz to 178 MHz frequency reference by using an integral frequency synthesizer consisting of a phase-locked loop circuit with a divider in the loop. Diagnostic loopback (transmitter to receiver) and line loopback (receiver to transmitter) is provided. See Other Operating Modes. The bypass signal selects between the BYPASSCLK and the VCO clock. BYPASSCLK can be used to provide an alternative clock to the internal VCO when the user selects an error correcting capability which is not provided by the S3067 dividers. The user must provide the required frequency for the BYPASSCLK when error-correcting capability of 6/5/4/3 bytes per 255-byte block is selected.
Timing Generator
The timing generation function, seen in Figure 4, provides a divide-by-16 version of the transmit serial clock. This circuitry also provides an internally generated load signal, which transfers the PIN[15:0] data from the parallel input register to the serial shift register. The PCLK output is a divide-by-16 rate version of transmit serial clock (divide-by-16). PCLK is intended for use as a divide-by-16 clock for upstream multiplexing and overhead processing circuits. Using PCLK for upstream circuits will ensure a stable frequency and phase relationship between the data coming into and leaving the S3067 device. The timing generator also produces a feedback reference clock to the clock synthesizer. A counter divides the synthesized clock down to the same frequency as the reference clock REFCLK. The PLL in the clock synthesizer maintains the stability of the synthesized clock by comparing the phase of the internal clock with that of the Reference Clock (REFCLK).
Clock Synthesizer
The clock synthesizer, shown in the block diagrams of Figures 4 and 5, is a monolithic PLL that generates the serial output clock frequency locked to the input Reference Clock (REFCLKP/N). The REFCLKP/N input must be generated from a crystal oscillator that has a frequency accuracy better than the value stated in Table 10 in order for the TSCLK frequency to have the accuracy required for operation in a SONET system. Lower-accuracy crystal oscillators may be used in applications less demanding than SONET/SDH. The on-chip PLL consists of a phase detector, which compares the phase relationship between the VCO output and the REFCLKP/N input, a loop filter which converts the phase detector output into a smooth DC voltage, and a VCO, whose frequency is varied by this voltage.
Table 5. Reference Jitter Limits
Operating Mode STS-48 STS-24 STS-12 STS-3 Band Width 12 kHz to 20 MHz 12 kHz to 10 MHz 12 kHz to 5 MHz 12 kHz to 1 MHz RMS Jitter -61 dBc 2 ps 4 ps 16 ps
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Parallel-to-Serial Converter
The parallel-to-serial converter shown in Figure 4 is comprised of a FIFO and a parallel-to-serial register. The FIFO input latches the data from the PIN[15:0] bus on the rising edge of PICLK. The parallel-toserial register is a loadable shift register which takes its parallel input from the FIFO output. An internally generated divide-by-16 clock, which is phase aligned to the transmit serial clock as described in the Timing Generator description, activates the parallel data transfer between registers. The serial data is shifted out of the parallel-to-serial register at the TSCLK rate.
S3067
FIFO
A FIFO is added to decouple the internal and external (PICLK) clocks. The internally generated divide-by-16 clock is used to clock out data from the FIFO. PHINIT and LOCKDET are used to center or reset the FIFO. The PHINIT and LOCKDET signals will center the FIFO after the third PICLK pulse. This is to insure that PICLK is stable. This scheme allows the user to have an infinite PCLK-to-PICLK delay through the ASIC. Once the FIFO is centered, the PCLK-to-PICLK delay can have a maximum drift as specified in Table 20.
internally generated clock is the same, their phase relationship is arbitrary. To prevent errors caused by short setup or hold times between the two timing domains, the timing generator circuitry monitors the phase relationship between PICLK and the internally generated clock. When a potential setup or hold time violation is detected, the phase error goes high. When PHERR conditions occur, PHINIT should be activated to recenter the FIFO (at least 2 PCLK periods). This can be done by connecting PHERR to PHINIT. When realignment occurs, up to 10 bytes of data will be lost. The user can also take in the PHERR signal, process it and send an output to PHINIT in such a way that idle bytes are lost during the realignment process. PHERR will go inactive when the realignment is complete.
Receiver Operation
The S3067 receiver chip provides the first stage of digital processing of a receive SONET STS-48/STS24/STS-12/STS-3/GBE/FC bit-serial stream. The bit-serial data stream is then converted into a 16-bit half-word data format. A loopback mode is provided for diagnostic loopback (transmitter to receiver). A line loopback (receiver to transmitter) is also provided. Both line and local loopback modes can be active at the same time.
FIFO Initialization
The FIFO can be initialized in one of the following three ways: 1. During power up, once the PLL has locked to the reference clock provided on the REFCLK pins, the LOCKDET will go active and initialize the FIFO. 2. When RSTB goes active, the entire chip is reset. This causes the PLL to go out of lock and thus the LOCKDET goes inactive. When the PLL reacquires the lock, the LOCKDET goes active and initializes the FIFO. Note: PCLK is held reset when RSTB is active. 3. The user can also initialize the FIFO by raising PHINIT. During the normal running operation, the incoming data is passed from the PICLK timing domain to the internally generated, divide-by-16 clock timing domain. Although the frequency of PICLK and the
Serial-to-Parallel Converter
The serial-to-parallel converter consists of two 16-bit registers. The first is a serial-in, parallel-out shift register, which performs the serial-to-parallel conversion clocked by the clock recovery block. On the falling edge of the POCLK, the data in the parallel register is transferred to an output parallel register which drives POUT[15:0].
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input is low, a loopback from the transmitter to the receiver at the serial data rate can be set up for diagnostic purposes. The differential serial output data from the transmitter is routed to the serial-toparallel block in place of the normal data stream (RSD). TSD/TSCLK outputs are active. DLEB takes precedence over SDPECL and SDTTL.
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S3067
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Squelched Clock Operation
Some integrated optical receiver/clock recovery modules force their recovered serial receive clock output to the logic zero state if the optical signal is removed or reduced below a fixed threshold. This condition is accompanied by the expected deassertion of the Signal Detect (SD) output. The S3067 has been designed for operation with clock recovery devices that provide continuous serial clock for seamless downstream clocking in the event of optical signal loss. For operation with an optical transceiver that provides the Squelched Clock behavior as described above, the S3067 can be operated in the Squelched Clock mode by activating the SQUELCH pin. In this condition, the Receive Serial Clock (RSCLKP/N) is used for all receiver timing when the SDLVPECL/ SDTTL inputs are in the active state. When the SDLVPECL/SDTTL inputs are placed in the inactive state (usually by the deassertion of LOCKDET or Signal Detect from the optical transceiver/clock recovery unit), the transmitter serial clock will be used to maintain timing in the receiver section. This will allow the POCLK to continue to run and the parallel outputs to flush out the last received characters and then assume the all-zero state imposed at the serial data input. It is important to note that in this mode there will be a one-time shortening or lengthening of the POCLK cycle, resulting in an apparent phase shift in the POCLK at the deassertion of the SD condition. Another similar phase shift will occur when the SD condition is reasserted. In the normal operating mode, with SQUELCH inactive, there will be no phase discontinuities at the POCLK output during signal loss or reacquisition (assuming operation with continuous clocking from the CRU device such as the AMCC S3076).
Line Loopback
The line loopback circuitry selects the source of the data and clock which is output on TSD and TSCLK. When the Line Loopback Enable input (LLEB) is high, it selects data and clock from the parallel-toserial converter block. When LLEB is low, it forces the output data multiplexer to select the data and clock from the RSD and RSCLK inputs, and a receive-to-transmit loopback can be established at the serial data rate. Diagnostic loopback and line loopback can be active at the same time.
Loop Timing
In Serial Loop Timing mode (SLPTIME), the clock synthesizer PLL of the S3067 is bypassed, and the timing of the entire transmitter section is controlled by the Receive Serial Clock, RSCLKP/N. This mode is entered by setting the SLPTIME input to a TTL high level. In this mode, the REFCLKP/N input is not used, and the RATESEL input is ignored for all transmit functions. It should be carefully noted that the internal PLL continues to operate in this mode and continues as the source for the 19MCK and 155MCK. Therefore these signals are being used (e.g. as the reference for an external S3076 clock recovery device), the REFCLKP/N and RATESEL inputs must be properly driven. In Reference Loop Timing mode (RLPTIME), the Parallel Clock from the receiver (POCLK) is used as the reference clock to the transmitter. In this mode, the REFCLKP/N input is not used. The 19MCK and 155MCK are generated from the POCLK in this operating mode. When operating the S3067 in RLPTIME mode, the 19MCK and 155MCK outputs should not be used as the back-up reference clock for a clock and data recovery device (S3066, S3040). When performing loopback testing (DLEB), the S3067 must not be in RLPTIME.
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MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Table 6. S3067 Transmitter Pin Assignment and Descriptions
Pin Name PIN0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 PIN8 PIN9 PIN10 PIN11 PIN12 PIN13 PIN14 PIN15 PICLKP PICLKN Level Single Ended LVPECL I/O I Pin # A2 B3 B2 C3 A1 C2 B1 D2 E3 C1 E2 F3 F2 E1 F1 G3 A4 A3 Description
S3067
Parallel Data Input. A divide-by-16, aligned to the PICLK, parallel input clock. PIN[15] is the most significant bit (corresponding to bit 1 of each PCM word, the first bit transmitted). PIN[0] is the least significant bit (corresponding to bit 16 of each PCM word, the last bit transmitted). PIN[15:0] is sampled on the rising edge of PICLK.
Internally Biased Diff. LVPECL Analog
I
Parallel Input Clock. A divide-by-16, nominally 50% duty cycle input clock, to which PIN[15:0] is aligned. PICLK is used to transfer the data on the PIN inputs into a holding register in the parallel-to-serial converter. The rising edge of PICLK samples PIN[15:0]. Loop Filter Capacitor. The external loop filter capacitor and resistors are connected to these pins. See Figure 26. Single-ended LVPECL input reference voltage.
CAP1 CAP2 IVREF
I
R5 T5 C4
DC
I
PHINIT
Single Ended LVPECL Diff. CML Diff. CML Diff. LVPECL Single Ended LVPECL
I
G2
Phase Initialization. Rising edge will realign internal timing.
TSDP TSDN TSCLKP TSCLKN PCLKP PCLKN PHERR
O
R11 R12 R8 R9 C6 B6 A5
Transmit Serial Data. Differential CML serial data stream signals, normally connected to an optical transmitter module. Transmit Serial Clock. Differential CML TSCLKP/N can be used to retime the TSD signal. This clock frequency will be selected by RATESEL and FECSEL. A reference clock generated by dividing the internal bit clock by 16. It is normally used to coordinate word-wide transfers between upstream logic and the S3067 device. Phase Error. Pulses High during each PCLK cycle for which there is a potential set-up/hold timing violation between the internal byte clock and PICLK timing domains. PHERR is updated on the falling edge of the PCLK outputs.
O
O
O
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MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Table 7. S3067 Receiver Pin Assignment and Descriptions
Pin Name RSDP RSDN SDLVPECL Level Diff. CML Single Ended LVPECL I/O I Pin # H15 G15 N16 Description Differential CML Receive Serial Data stream signals normally connected to an optical receiver module. Internally biased and terminated. LVPECL Signal Detect. LVPECL with internal pull-down. Active High when SDTTL is held at logic 0. A single-ended 10K LVPECL input to be driven by the external optical receiver module to indicate a loss of received optical power. When SDLVPECL is inactive, the data on the Receive Serial Data In (RSDP/N) pins will be internally forced to a constant zero. When SDLVPECL is active, data on the RSDP/N pins will be processed normally. When SDTTL is to be connected to the optical receiver module instead of SDLVPECL, then SDLVPECL should be tied High to implement an active Low Signal Detect, or left unconnected to implement an active High Signal Detect. LVTTL Signal Detect. Active High when SDLVPECL is unconnected (logic 0). Active Low when SDLVPECL is held at logic 1. A single-ended LVTTL input to be driven by the external optical receiver module to indicate a loss of received optical power. When SDTTL is inactive, the data on the RSDP/N pins will be internally forced to a constant zero. When SDTTL is active, data on the RSDP/N pins will be processed normally. Receive Serial Clock. Used to supply a clock input for the RSDP/N inputs. Internally biased and terminated. Parallel data output bus, a divide by 16, aligned to the POCLK parallel output clock. POUT15 is the most significant bit (corresponding to bit 1 of each PCM word, the first bit received). POUT0 is the least significant bit. POUT[15:0] is updated on the falling edge of POCLK.
I
SDTTL
LVTTL
I
P16
RSCLKP RSCLKN POUT0 POUT1 POUT2 POUT3 POUT4 POUT5 POUT6 POUT7 POUT8 POUT9 POUT10 POUT11 POUT12 POUT13 POUT14 POUT15 POCLKP POCLKN OVREF
Diff. CML Single Ended LVPECL
I O
L15 K15 F14 E16 D16 E14 C16 D15 D14 C15 B15 A14 C13 A13 C12 B12 C11 B11 B1 0 C10 B14
Diff. LVPECL DC
O
Parallel Output Clock. A divide by 16, nominally 50% duty cycle, output clock that is aligned to POUT [15:0] word serial output data. POUT[15:0] is updated on the falling edge of POCLK. Single-ended LVPECL reference voltage. Tracks midswing voltage of parallel output data bus.
O
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MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Table 8. S3067 Common Pin Assignment and Descriptions
Pin Name SQUELCH Level LVTTL I/O I Pin # R16 Description
S3067
RSCLK Clock Squelch. Active High. When SQUELCH is active and SD is inactive, the transmit clock will be used in place of the RSCLK. Reference Clock Input. Used as the reference for the internal bit clock frequency synthesizer.
REFCLKP REFCLKN
Internally Biased Diff. LVPECL LVTTL
I
M2 L3
DLEB
I
N15
Diagnostic Loopback Enable. Active Low. Selects diagnostic loopback. When DLEB is High, the S3067 device uses the primary data (RSD) and clock (RSCLK) inputs. When Low, the S3067 device uses the diagnostic loopback clock and data from the transmitter. TSD/TSCLK are active in DLEB. Line Loopback Enable. Active Low. Selects line loopback. When LLEB is Low, the S3067 will route the data from the RSD/RSCLK inputs to the TSD/TSCLK outputs. Kill Receive Clock Input. For normal operation, KILLRXCLK is High. When this input is Low, it will force POCLK output to a logic "0" state. Serial Clock Loop Time Select input. Active High. When High, SLPTIME enables the recovered clock from the receive section to be used in place of the synthesized transmit clock. Reference Clock Looptime Select input. Active High. When High, RLPTIME enables POCLK from the receiver to be used as the reference clock input to the transmitter. Master Reset. Reset input for the device, Active Low. During Reset, all clocks are disabled. Test Enable. Used for production testing. Low for normal operation. VCO / by 16 Clock Output from the clock synthesizer. This output should be connected to the reference clock input of the external clock recovery function (such as the S3066). It is recommended to tie 155MCKP/N to VCC when not used. VCO / by 128 Clock Output from the clock synthesizer. This output should be connected to the reference clock input of the external clock recovery function. It is recommended to tie 19MCK to VCC when not used. Lock Detect. Active High. Goes active after the PLL has locked to the clock provided on the REFCLK pins. LOCKDET is an asynchronous output.
LLEB
LVTTL
I
N14
KILLRXCLK
LVTTL
I
M1 4
SLPTIME
LVTTL
I
T1
RLPTIME
LVTTL
I
T2
RSTB TESTEN 155MCKP 155MCKN
LVTTL LVTTL Diff. LVPECL
I I O
P15 N2 R14 T15
19MCK
Single Ended LVPECL LVTTL
O
P14
LOCKDET
O
H1
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MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Table 8. S3067 Common Pin Assignment and Descriptions (Continued)
Pin Name RATESEL0 RATESEL1 BYPASSCLKP BYPASSCLKN BYPASS FECSEL [2:0] AGND AVCC LVPECLPOW Level LVTTL Differential CML LVTTL LVTTL GND +3.3V +3.3V I/ O I I I I Pin # R2 P3 K2 J2 M3 R1, P2, N3 P4, P5, R4, R6, T6 P6, T3, T4 Description
.. Rate Select. Selects the operating mode. (See Table 2.)
Bypass Clock. Provides an alternative serial clock bypassing the internal VCO. Active High. Selects between BYPASS clock and the VCO clock. FEC Select. Selects the error corrrecting capability. (See Table 3.) Ground (0V) Power Supply
A6, A10, A12, Power Supply B4, C14, D1, E15, G14, J1, K3, L14, N1, P8, P9, P10, P12, R15 A11, B5, B13, Ground (0V) B16, C5, D3, F15, F16, G1, H2, H14, J3, K14, M1, P7, R7, T14 A7, A9, J16, L2, P13 A8, B8, K16, L1, T13 P1, T16 M15, R3 T7, T9 R10, T12 Power Supply Ground (0V) Power Supply Ground (0V) Ground (0V) Ground (0V)
LVPECLGND
GND
COREPOW COREGND TTLPOW TTLGND TCGND TDGND NC
+3.3V GND +3.3V GND GND GND
A15, A16, B7, Not Connected B9, C7, C8, C9, H3, G16, H16, J14, J15, K1, L16, M16, P11, R13, T8, T10, T11
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MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Figure 6. S3067 Pinout-Bottom View
A B C D E F G H J K L M N P R
S3067
T
1
PIN4
P IN 6
PIN9
LVPECL P OW
PIN13
PIN14
LVPECL LVPECL LOCKDET GND POW LVPECL GND BYPASS CLKN LVPECL GND
NC
CORE GND CORE POW
LVPECL GND
LVPECL POW
TTLPOW FECSEL2 SLPTIME
2
PIN0
P IN 2
PIN5
PIN7
PIN10
PIN12
PHINIT
BYPASS CLKP LVPECL POW
REFCLKP TESTEN
FECSEL1
RATE SEL0
RLPTIME
3
PICLKN
PIN1
PIN3
LVPECL GND
PIN8
PIN11
PIN15
NC
REFCLKN BYPASS
FECSEL0
RATE SEL1
TTLGND
AVCC
4
PICLKP
LVPECL POW LVPECL GND
IVREF
AGND
AGND
AVCC
5
PHERR
LVPECL GND
AGND
CAP1
CAP2
6
L V P E CL POW CORE POW CORE GND CORE POW L V P E CL P OW L V P E CL GND L V P E CL P OW
PCLKN
PCLKP
AVCC
AGND
AGND
7
NC
NC
LVPECL GND LVPECL POW LVPECL POW LVPECL POW
LVPECL GND
TCGND
8
CORE GND
NC
TSCLKP
NC
156 Pin TBGA
NC
9
NC
BOTTOM VIEW
TSCLKN
TCGND
10
POCLKP
POCLKN
TDGND
NC
11
POUT15
POUT14
NC
TSDP
NC
12
POUT13
POUT12
LVPECL POW CORE POW LVPECL POW L V P E CL GND LVPECL GND LVPECL POW K IL L RX CLK
TSDN
TDGND
13
POUT11
LVPECL GND
POUT10
NC
CORE GND LVPECL GND
14
POUT9
OVREF
LVPECL POW
POUT6
POUT3
POUT0
NC
LLEB
19MCK
155MCKP
15
NC
POUT8
POUT7
POUT5
LVPECL POW
LVPECL GND LVPECL GND
RSDN
RSDP
NC
RSCLKN
RSCLKP
TTLGND
DLEB
RSTB
L V P E CL POW
155MCKN
16
NC
LVPECL GND
POUT4
POUT2
POUT1
NC
NC
CORE POW
CORE GND
NC
NC
SDLV PECL
SDTTL
SQUELCH TTLPOW
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MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Figure 7. S3067 Pinout-Top View
T R P N M L K J H G F E D C B A
SLPTIME FECSEL2 TTLPOW
LVPECL POW
LVPECL GND
CORE GND CORE POW
NC
LVPECL LVPECL LOCKDET POW GND BYPASS CLKN LVPECL GND LVPECL GND
PIN14
PIN13
LVPECL POW
PIN9
PIN6
PIN4
1
RLPTIME
RATE SEL0
FECSEL1
TESTEN
REFCLKP
BYPASS CLKP LVPECL POW
PHINIT
P I N1 2
PIN10
PIN7
PIN5
PIN2
PIN0
2
AVCC
TTLGND
RATE SEL1
FECSEL0
BYPASS REFCLKN
NC
PIN15
PIN11
PIN8
L V P E CL GND
PIN3
PIN1
PICLKN
3
AVCC
A GN D
AGND
IVREF
LVPECL POW LVPECL GND
PICLKP
4
CAP2
CAP1
AGND
LVPECL GND
PHERR
5
AGND
AGND
AVCC
PCLKP
PCLKN
LVPECL POW CORE POW CORE GND CORE POW LVPECL POW LVPECL GND LVPECL POW
6
TCGND
LVPECL GND
LVPECL GND LVPECL POW LVPECL POW LVPECL POW
NC
NC
7
NC
TSCLKP
156 Pin TBGA TOP VIEW
NC
CORE GND
8
TCGND
TSCLKN
NC
NC
9
NC
TDGND
POCLKN
POCLKP
10
NC
TS D P
NC
POUT14
POUT15
11
TDGND
TS D N
LVPECL POW CORE POW KILLRX CLK LVPECL POW L V P E CL GND LVPECL GND LVPECL POW
POUT12
POUT13
12
CORE GND LVPECL GND
NC
POUT10
LVPECL GND
POUT11
13
155MCKP
19MCK
LLEB
NC
POUT0
POUT3
POUT6
L V P E CL P OW
OVREF
POUT9
14
155MCKN
LVPECL POW
RSTB
DLEB
TTLGND
RSCLKP
RSCLKN
NC
RSDP
RSDN
LVPECL GND LVPECL GND
LVPECL POW
POUT5
POUT7
POUT8
NC
15
TTLPOW SQUELCH
SDTTL
SDLV PECL
NC
NC
CORE GND
CORE POW
NC
NC
POUT1
POUT2
POUT4
LVPECL GND
NC
16
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September 17, 2002/ Revision A
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Figure 8. 156 Pin TBGA Package
S3067
Table 9. Thermal Management
Device S3067 S3067 S3067 Max Package Power 2.5 W 2.5 W 2.5 W ja (Still Air) 18.6 C/W 15.8 C/W 14.57 C/W jc 1 C/W Conditions Commercial use only (0 to 70 C). Industrial use. 100 LFPM airflow. Industrial use (-20 to 85 C). HTS278D heatsink from chip coolers.
September 17, 2002/ Revision A
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MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Table 10. Performance Specifications
Parameter Nominal VCO Center Frequency Output Jitter STS-48 STS-24/Gigabit Ethernet (Not tested) STS-12 STS-3 Reference Clock Frequency Tolerance Reference Clock Input Duty Cycle Reference Clock Rise and Fall Times -100 Min 2.10 Typ Max 2.67 Units GHz Note: Output jitter measured at SONET operating rate using appropriate filter. UI (rms) rms jitter, in lock. 20 is required to meet SONET output frequency specification. Conditions
0.005 0.005 0.005 0.005 +100
ppm
45
55 1.5
% ns 10% to 90% of amplitude.
Table 11. Absolute Maximum Ratings
Parameter Storage Temperature Voltage on VCC with respect to GND Voltage on any LVPECL Input Pin High Speed LVPECL Output Source Current Min -65 -0.5 0 Typ Max 150 +3.6 VCC 24 Units C V V mA
ESD Ratings The S3067 is rated to the following voltages based on the human body model: 1. All pins are rated above 200 V.
Table 12. Recommended Operating Conditions
Parameter Ambient Temperature Under Bias Voltage on VCC with respect to GND Voltage on any LVPECL Input Pin Voltage on any LVTTL Input Pin ICC
1
Min -20 3.135 VCC -2 0
Typ
Max 85
Units C V V V mA
3.3
3.465 VCC VCC
455
606
1. Outputs unterminated.
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Table 13. LVTTL Input/Output DC Characteristics
Parameter VIH VIL IIH IIL VOH VOL Description Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage -500 2. 4 0.5 Min 2.0 0.0 Typ Max TTL VCC 0.8 50 Units V V A A V V
S3067
Conditions TTL VCC = Max TTL VCC = Max VIN = 2.4 V VIN = 0.5 V VCC= Min IOH = -100 A VCC = Min IoL = 1.5 mA
Table 14. Internally Biased Differential LVPECL Input DC Characteristics
Parameter VIL VIH VINDIFF VINSINGLE VBIAS Description LVPECL Input Low LVPECL Input High Diff. Input Voltage Swing Single Ended Input Voltage Swing Input DC Bias Min VCC -2.0 VCC -1.25 400 200 VCC -0.65 VCC -0.5 Typ Max VCC -1.4 VCC -0.55 2400 1200 VCC -0.35 Units V V mV mV V See Figure 13. See Figure 13. Conditions
Table 15. Differential LVPECL Output DC Characteristics
Parameter VOUTSINGLE VOUTDIFF VOH VOL Description Single Ended Output Voltage Swing Diff. Output Voltage Swing Output High Voltage Output Low Voltage Min 500 1000 VCC -1.2 VCC -1.95 Typ Max 950 1900 VCC -0.65 VCC -1.50 Units mV mV V V Conditions 51 to VCC-2. See Figure 13. 51 to VCC-2. See Figure 13. 51 to VCC-2 51 to VCC-2
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MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Table 16. Single-Ended LVPECL Input DC Characteristics1
Parameters VIL VIL VIH VIH IVREF II for IVREF Description PECL Input Low Voltage PECL Input Low Voltage PECL Input High Voltage PECL Input High Voltage Single-Ended LVPECL DC Bias Voltage Maximum Input Current Min VCC -2.0 VCC -2.0 VCC -1.2 VCC -1.023 VIL +180 500 Typ Max VCC -1.5 VCC -1.441 VCC -0.75 VCC -0.55 VIH -180 750 Units V V V V mV A Conditions Guaranteed at -20 C. Guaranteed at 85 C. Guaranteed at -20 C. Guaranteed at 85 C.
1. The AMCC LVPECL inputs (VIL and VIH) are non-temperature compensated I/O which vary at 1.3 mV/C
Table 17. Single-Ended LVPECL Output DC Characteristics1
Parameters VOL VOL VOH VOH OVREF IO for OVREF Description PECL Output Low Voltage PECL Output Low Voltage PECL Output High Voltage PECL Output High Voltage Single-Ended LVPECL DC Bias Voltage Maximum Output Current Min VCC -1.98 VCC -1.98 VCC -1.1 VCC -0.95 VCC -1.6 500 Typ Max VCC -1.63 VCC -1.57 VCC -0.850 VCC -0.673 VCC -1.20 750 V A V Units V Conditions Guaranteed at -20 C. Guaranteed at 85 C. Guaranteed at -20 C. Guaranteed at 85 C. (VOH -OVREF)MIN>250 mV (OVREF -VOL)MIN>250 mV
1. The AMCC LVPECL outputs are non-temperature compensated I/O which vary at 1.3 mV/C
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Table 18. CML Output DC Characteristics
Parameter VOL (Data) VOH (Data) VOUTDIFF (Data) VOUTSINGLE (Data) VOL (Clock) VOH (Clock) VOUTDIFF (Clock) VOUTSINGLE (Clock) Description CML Output Low Voltage CML Output High Voltage CML Serial Output Differential Voltage Swing CML Serial Output Single-ended Voltage Swing CML Output Low Voltage CML Output High Voltage CML Serial Output Differential Voltage Swing CML Serial Output Single-ended Voltage Swing Min VCC -1.0 VCC -0.35 800 400 VCC -1.5 VCC -0.5 800 400 Typ Max VCC -0.65 VCC -0.2 1600 800 VCC -0.85 VCC -0.25 1800 900 Units V V mV mV V V mV mV
S3067
Condition 100 line to line. 100 line to line. 100 line to line. See Figure 13. 100 line to line at 2.5 Gbps. See Figure 13. 100 line to line. 100 line to line. 100 line to line. See Figure 13. 100 line to line at 2.5 GHz. See Figure 13.
Table 19. CML Input DC Characteristics
Parameter VIL VIH VINDIFF VINSINGLE RDIFF Description CML Input Low CML Input High Differential Input Voltage Swing Single-ended Input Voltage Swing Differential Input Resistance Min VCC -1.7 VCC -0.55 300 150 80 100 Typ Max VCC -0.6 VCC -0.15 2400 1200 120 Units V V mV mV See Figure 13. See Figure 13. Conditions
September 17, 2002/ Revision A
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S3067
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Table 20. Transmitter AC Timing Characteristics
Parameter TSCLK Frequency BYPASS Clock Frequency TSCLK Duty Cycle TSCLK Duty Cycle Distortion w.r.t. RSCLK or BYPASSCLK (In SLPTIME, LLEB or BYPASS modes) PICLK Duty Cycle tSPIN tHPIN tPCLK tSTSD tHTSD PIN [15:0] Set-up Time w.r.t. PICLK (See Figure 9) PIN [15:0] Hold Time w.r.t. PICLK (See Figure 9) PCLK to PICLK drift after the FIFO is centered TSD Set-up Time w.r.t. TSCLK Rising (See Figure 9) TSD Hold Time w.r.t. TSCLK Rising (See Figure 9) PCLKP/N Duty Cycle 100 100 45 55 35 1.5 0.5 5.2 43 Description Min Max 2.7 2.7 57 5.0 65 Units GHz GHz % % % ns ns ns ps ps %
Figure 9. Transmitter Input Timing1
PICLKP tSPIN tHPIN
Figure 10. Transmitter Output Timing1
TSCLKP tSTSD tHTSD
TSD
PIN[15:0]
Notes on High-Speed Timing: 1. Timing is measured from the cross-over point of the reference signal to the 50% level of the input/output.
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Table 21. AC Receiver Timing Characteristics
Symbol Description POCLK Duty Cycle tPPOUT tSPOUT tSPOUT tHPOUT tSRSD tHRSD POCLK Low to POUT [15:0] Valid Prop. Delay (See Figure 12) POUT [15:0] Set-Up Time w.r.t. POCLK (2.1 GHz - 2.488 GHz) (See Figure 11) POUT[15:0] Set-up Time w.r.t. POCLK (2.488 - 2.67 GHz) (See Figure 11) POUT[15:0] Hold Time w.r.t. POCLK (See Figure 11) RSD Set-up Time w.r.t. RSCLK (See Figure 11) RSD Hold Time w.r.t. RSCLK (See Figure 11) RSCLK Duty Cycle RSCLK Frequency Min 45 -1.8 2.25 2 2 75 75 40 60 2.7 Max 55 +1.8
S3067
Units % ns ns ns ns ps ps % GHz
Figure 11. Receiver Input Timing Diagram1
RSCLKP tSRSD RSD
Notes on High-Speed LVPECL Input Timing: 1. Timing is measured from the cross-over point of the reference signal to the 50% level of the output.
tHRSD
Figure 12. Receiver Output Timing Diagram1
POCLKP tP POUT POUT[15:0] tS POUT tHPOUT
Notes on High-Speed LVPECL Input Timing: 1. Timing is measured from the cross-over point of the reference signal to the 50% level of the output.
September 17, 2002/ Revision A
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S3067
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Figure 13. Differential Voltage Measurement
V(+) VSWING V(-)
V(+) - V(-)
VD = 2 X VSWING 0.0V
Note: V(+) - V(-) is the algebraic difference of the input signals.
Figure 14. Phase Adjust Timing1
4-10 BYTE CLOCKS
2 BYTE CLOCKS
PHERR PHINIT
PCLKP
PICLKP
TRANSFER CLK (Internal)
1. Byte Clock = 155.52 MHz
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September 17, 2002/ Revision A
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Figure 15. S3076 to S3067 Differential CML Input Termination
S3067
+3.3 V Zo=50
+3.3 V Vcc -0.5 V
100
Zo=50 S3076 SERDATOP/N SERCLKOP/N
Vcc -0.5 V S3067 RSDP/N RSCLKP/N
Figure 16. +5V Differential CML Driver to S3067 Differential CML Input AC Coupled Termination
+5 V 0.01 F Zo=50
+3.3 V Vcc -0.5 V
100
0.01 F SERDATOP/N SERCLKOP/N
Zo=50
Vcc -0.5 V S3067 RSDP/N RSCLKP/N
Figure 17. Single-Ended LVPECL Driver to S3067 Single-Ended LVPECL Input Termination
+3.3 V Zo=50
+3.3 V 130 82 IVREF S3067 PIN[15:0] PHINIT +3.3 V
OVREF
0.01 F
September 17, 2002/ Revision A
23
S3067
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Figure 18. S3067 Differential CML Output to +5V PECL Input AC Coupled Termination
+3.3 V
0.01 F
Zo=50 100
+5 V
0.01 F S3067 TSDP/N TSCLKP/N
Zo=50
Figure 19. S3067 Single-Ended LVPECL Driver to Single-Ended LVPECL Input Termination
+3.3 V Zo=50
3.3 V 130 82 +3.3 V
S3067
POUT[15:0] PHERR OVREF
0.01 F
Figure 20. S3067 Single-Ended LVPECL Driver to Single-Ended LVPECL Input Termination
+3.3 V Zo=50 51 Vcc-2 V S3067
POUT[15:0] PHERR OVREF
+3.3 V
0.01 F
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September 17, 2002/ Revision A
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Figure 21. S3067 Single-Ended LVPECL Driver to Differential LVPECL Input Termination
S3067
+3.3 V Zo=50 200 0.1 F 100 100
+3.3 V
S3067 POUT[15:0] PHERR
AMAZON S4801
Figure 22. S3067 Differential LVPECL Driver to Differential LVPECL Input Termination
+3.3 V
Zo=50 Vcc-2 Zo=50 51 Vcc-2 51
+3.3 V
S3067 PCLKP/N POCLKP/N
Figure 23. S3067 Differential LVPECL Driver to Differential LVPECL Input Termination
+3.3 V
Zo=50 130 Zo=50 82
130 82
+3.3 V
S3067 PCLKP/N POCLKP/N
September 17, 2002/ Revision A
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S3067
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Figure 24. S3067 Differential LVPECL Driver to Differential LVPECL Input Termination1
+3.3 V 200 200 S3067 PCLKP/N POCLKP/N
Zo=50 100 Zo=50
+3.3 V
1. With 100 line to line, VOL Max increases by 100 mV .
Figure 25. Differential LVPECL Driver to S3067 Internally Biased Differential LVPECL Inputs
+3.3 V
VCC -0.5 V
Zo=50 100 Zo=50
+3.3 V
VCC -0.5 V
S3067 PICLKP/N REFCLKP/N
Figure 26. External Loop Filter Components
10 F
1 k CAP1 CAP2
1 k
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September 17, 2002/ Revision A
MULTIRATE (OC-48/24/12/3/GBE/FC) SONET/SDH/ATM TRANSCEIVER w/ FEC
Ordering Information
PREFIX DEVICE PACKAGE Revision
S3067
S - Integrated Circuit
3067
TB - 156 TBGA
20
X Prefix
XXXX Part No.
XX Package
XX Revision (S3067TB20)
IS
O 90 0
D
1
IFI
Applied Micro Circuits Corporation * 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 * (800) 755-2622 * Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 2002 Applied Micro Circuits Corporation D476/R1608
September 17, 2002/ Revision A
E
CE
RT
27

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